The present invention relates to a sense amplifier which detects an electric current flowing through a selected memory cell to read data written therein.
As a conventional sense amplifier, there is known one which detects an electric current flowing through a memory cell selected in, for example, a ROM (Read Only Memory) thereby to read data written therein. This sense amplifier comprises a current sense circuit which detects an electric current that flows through each of memory cell arrays arranged in matrix form, a current sense circuit for comparison, which detects an electric current flowing through a memory cell array for comparison, and a comparator or comparison circuit.
Both of patent documents 1 (Japanese Unexamined Patent Publication No. Hei 8(1996)-77779) and 2 (Japanese Unexamined Patent Publication No. 2004-206860) disclose a current detection type sense amplifier. Particularly described in the patent document 2 is a read circuit aimed at reading data at high speed and low current consumption by selecting a memory cell when a clock signal is “H” and varying a reference voltage according to data of the selected memory cell when the clock signal is “L”.
In the conventional sense amplifiers of the patent documents 1 and 2 and the like, however, the electric currents that flow through the current sense circuit, the current sense circuit for comparison and the comparison circuit are cut off using a chip selection signal upon a standby state with a view toward reducing current consumption. Therefore, when the sense amplifier is switched to its normal operating state by the chip selection signal, there is a need to counterbalance the two current sense circuits and provide the time required to reach a proper operating state of the sense amplifier.